1. Field
The present disclosure generally relates to a multiplying delay-locked-loop (MDLL) circuit. More specifically, the present disclosure relates to an MDLL that includes a phase interpolator which adjusts aperture timing for the MDLL.
2. Related Art
Timing circuits are widely used in electronic devices and systems to generate signals and to synchronize the operation of components. One type of existing timing circuit is a multiplying delay-locked loop (MDLL), such as MDLL 100 shown in FIG. 1. In this MDLL, each rising edge of the input reference clock signal (rclk) enters an inverting delay line via a multiplexer. After each edge passes, the multiplexer switches to select the output of the delay element, thereby connecting the circuit into a ring oscillator. Furthermore, after passing M−1 rising edges (and the preceding falling edges) in this configuration, selection control logic produces a selection pulse (sel) that switches the multiplexer back to route the next rising edge on rclk into the delay element. When this next edge arrives, it is compared against the rising edge on output clock signal (bclk) using a phase detector (which is shown as a D-flip flop in FIG. 1), and the delay-element control voltage (vctrl) is adjusted to align the two edges. Note that once the loop is locked M pulses are generated on bclk for each input pulse on rclk, and the rising edge of each Mth output pulse is aligned with the rising edge of each input pulse.
This MDLL design offers several advantages. Notably, each rising edge of rclk zeros the phase error of the output bclk. Thus, MDLL 100 can avoid the phase-error accumulation that inherently occurs in a phase-locked loop (PLL). Furthermore, because a single delay element is used to generate the edges of bclk, there is no fixed pattern jitter due to device mismatch. In addition, the multiplication rate can be programmed by changing the number of cycles of bclk that are recirculated before the selection control logic switches the multiplexer.
However, several issues associated with the design of MDLL 100 typically require careful attention. In particular, the input rclk typically must be kept very clean, because any jitter on this signal will be passed directly to the output and will appear during a single cycle. (This is usually not a serious issue because inexpensive crystal oscillators have sufficiently low jitter for this application.) In addition, any mismatch in the phase of bclk and rclk will result in fixed-pattern jitter that occurs on every Mth bclk edge (where M is the multiplication ratio). Reducing this fixed pattern jitter to acceptable levels often requires a novel phase comparator design and careful attention to the design of the selection and multiplexing circuits.
A variety of techniques have been proposed to reduce the fixed pattern jitter. For example, in one proposed MDLL cycle-to-cycle jitter is filtered by applying the output signal from the MDLL to a replica slave oscillator, which is connected to the same control voltage. However, this technique often has the usual drawback of injection locking, i.e., the mismatch between the master and the slave oscillators requires the injection strength to be strong enough to guarantee locking, which usually limits the filtering quality.
In another proposed MDLL, an auxiliary loop is used to sense the pattern error, and a resulting error signal is added to the control voltage to correct for the pattern error. For example, in an analog implementation of the auxiliary loop, the error signal may be introduced as an offset to a charge pump to correct for the pattern error. Alternatively, in a digital auxiliary loop a gated ring oscillator may be used to measure the pattern error, and the control voltage may be adjusted based on this error.
In addition, in existing MDLLs it is assumed that the selection control logic can provide the sel pulse quickly enough to select the next reference edge. Moreover, the impact of the position or phase of the sel pulse with respect to the edge in rclk on the pattern jitter is typically not considered. However, there are gate delays associated with the selection control logic, which are a function of process, voltage and temperature variations. These gate delays can make it difficult to use MDLLs in high-frequency applications, and in particular in applications operating at more than 2 GHz.
Hence, what is needed is an MDLL without the above-described problems.